The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Dec. 18, 2023
Applicant:

Synaptics Incorporated, San Jose, CA (US);

Inventor:

Yutaka Saeki, Kanagawa, JP;

Assignee:

Synaptics Incorporated, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/155 (2006.01); H02M 1/00 (2006.01);
U.S. Cl.
CPC ...
H02M 1/0067 (2021.05); H02M 3/155 (2013.01);
Abstract

A mixed signal circuit includes a logic circuit, an analog circuit, a logic supply line, a first regulator circuit, and a second regulator circuit. The analog circuit is configured to receive an analog supply voltage. The logic supply line is coupled to the logic circuit. The first regulator circuit includes an output p-channel metal oxide semiconductor (PMOS) transistor having a drain coupled to the logic supply line and a first former stage configured to receive a first logic supply voltage to drive a gate of the output PMOS transistor. The second regulator circuit includes an output n-channel metal oxide semiconductor (NMOS) transistor having a source coupled to the logic supply line and a second former stage configured to receive the analog supply voltage to drive a gate of the output NMOS transistor. The analog supply voltage is higher than the first logic supply voltage.


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