The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Feb. 17, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Su Ji Um, Icheon-si, KR;

Min Hee Park, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/56 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 24/85 (2013.01); H01L 21/486 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/43 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H10B 80/00 (2023.02); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/43985 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/48471 (2013.01); H01L 2224/48993 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/8513 (2013.01); H01L 2224/85986 (2013.01); H01L 2924/1438 (2013.01);
Abstract

A method of manufacturing a semiconductor package of stacked semiconductor chips includes forming a reverse wire bond by bonding one end of a reverse wire to a chip pad of the second-highest semiconductor chip of the stacked semiconductor chips and connecting the other end of the reverse wire to a conductive bump on a chip pad of the uppermost semiconductor chip of the stacked semiconductor chips. The method also includes molding the stacked semiconductor chips with the reverse wire bond using a mold layer. The method further includes processing the mold layer to expose the conductive bump and the other end of the reverse wire in the reverse wire bond through an upper surface of the mold layer.


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