The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Nov. 28, 2022
Applicant:

Sonova Ag, Staefa, CH;

Inventor:

Anwar Hashmi, Staefa, CH;

Assignee:

Sonova AG, Staefa, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H04R 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/14 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H04R 25/609 (2019.05); H01L 24/13 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/14177 (2013.01); H01L 2224/14517 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/81801 (2013.01); H01L 2924/014 (2013.01);
Abstract

An exemplary hearing device includes a housing and a chip package disposed within the housing. The chip package may comprise a printed circuit board, an integrated circuit configured to perform an electronic function associated with the hearing device, and a plurality of solder bumps on a bottom surface of the integrated circuit. The plurality of solder bumps may provide conductive connectivity between the integrated circuit and the printed circuit board. The plurality of solder bumps may comprise a first group of solder bumps located within a center region of the bottom surface of the integrated circuit and a second group of solder bumps located within a peripheral region of the bottom surface, the peripheral region surrounding the center region. All signals required for the integrated circuit to perform the electronic function may be provided by way of the first group of solder bumps.


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