The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2026

Filed:

Jul. 02, 2021
Applicant:

Sumitomo Bakelite Co., Ltd., Tokyo, JP;

Inventors:

Takahiro Harada, Tokyo, JP;

Wataru Kosaka, Tokyo, JP;

Shinya Yamamoto, Tokyo, JP;

Atsunori Nishikawa, Tokyo, JP;

Masaharu Ito, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 23/04 (2006.01); H01L 23/367 (2006.01); H01L 23/532 (2006.01); H01L 25/07 (2006.01); H05K 1/09 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 23/04 (2013.01); H01L 23/367 (2013.01); H01L 23/5328 (2013.01); H01L 25/072 (2013.01); H05K 1/09 (2013.01);
Abstract

A power module () includes a power semiconductor chip () and a Cu circuit () having the power semiconductor chip () provided on one surface. The power module () includes: a sintering layer () joining the power semiconductor chip () and the Cu circuit () by using a sintering paste; and a heat dissipation sheet () provided for joining a Cu base plate () to the other surface of the Cu circuit (), in which in a first laminated structure in which the power semiconductor chip (), the sintering layer (), the Cu circuit (), and the heat dissipation sheet () are laminated, the total thermal resistance XA in the direction of lamination is equal to or less than 0.30 (K/W).


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