Pseudo multi-port memory with memory cells each having two-port memory cell architecture and multiple enable pulses on same wordline and associated memory access method

Abstract

A pseudo multi-port memory includes a memory array, a row decoder circuit, a timing controller circuit, a sense amplifier circuit, and a write driver circuit. The timing controller circuit outputs a timing control signal to the row decoder circuit, wherein during one memory clock cycle, the row decoder circuit is controlled by the timing control signal to make a read wordline (RWL) signal have an enable pulse and a write wordline (WWL) signal have multiple enable pulses. During one memory clock cycle, the sense amplifier circuit performs read operations upon a selected memory cell when the selected RWL is enabled by the enable pulse and the selected WWL is enabled by at least one first enable pulse, and the write driver circuit performs a write operation upon the selected memory cell when the selected WWL is enabled by one second enable pulse.