Optimized xor loading to sram and hmb

Abstract

Selectively writing relevant bins directly to a controller's volatile memory (e.g., SRAM) based on a next-to-write address and writing the remaining bins to a host's volatile memory (e.g., DRAM or HMB), avoids the need for any additional reads from host's volatile memory and writes from controller's volatile memory. Avoiding the need for any additional reads from host's volatile memory, which has a slower access time than controller's volatile memory, improves exit latency from the boot and low-power-state exit flows. Prior to writing the parity bins to the controller or the host, the controller may store parity bins and/or the next-to-write address in non-volatile memory. The next-to-write address is then evaluated to determine whether a party bin is written to the controller's volatile memory or the host's volatile memory.