Clock adjustment circuit using pattern filter circuit to select predetermined data patterns for phase error detection under acquisition mode and tracking mode and associated clock adjustment method

Abstract

A clock adjustment circuit includes a pattern filter circuit, a phase error detector (PED) circuit, and a phase error calculation circuit. The pattern filter circuit selects first predetermined data patterns from a plurality of consecutive data samples under an acquisition mode of the clock adjustment circuit, wherein the plurality of consecutive data samples are derived from an output of a first sampler circuit. The PED circuit detects phase errors according to an output of the pattern filter circuit and error samples derived from an output of a second sampler circuit. The phase error calculation circuit determines timing compensation of a sampling clock according to an output of the PED circuit, wherein the sampling clock is used by the first sampler circuit and the second sampler circuit.