The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jan. 05, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Youncheol Jeong, Hwaseong-si, KR;

Jaeung Koo, Yongin-si, KR;

Kwansung Kim, Yongin-si, KR;

Seungyoon Kim, Suwon-si, KR;

Boun Yoon, Seoul, KR;

Jooho Jung, Suwon-si, KR;

Sukbae Joo, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 21/02 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 84/85 (2025.01); H01L 21/0259 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 84/0167 (2025.01); H10D 84/017 (2025.01); H10D 84/0186 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01);
Abstract

A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure vertically overlapping the active region and the plurality of channel layers on the substrate, extending in a second direction, and including a gate electrode surrounding the plurality of channel layers and a gate capping layer disposed on an upper surface of the gate electrode, a first source/drain region disposed on a side of the gate structure on the active region and in contact with the plurality of channel layers, an isolation structure intersecting the active region on the substrate, extending in the second direction, and disposed between the first source/drain region and a second source/drain region adjacent to each other, and contact structures in contact with the source/drain regions.


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