The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Oct. 10, 2022
Hitachi Energy Ltd, Zürich, CH;
Stephan Wirths, Thalwil, CH;
Lars Knoll, Hägglingen, CH;
HITACHI ENERGY LTD, Zürich, CH;
Abstract
The present disclosure relates to a manufacturing method for a power semiconductor device (), comprising: forming multiple growth templates on a carrier substrate (), comprising at least a first plurality of hollow growth templates () and a second plurality of hollow growth templates (); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (), thereby forming a corresponding plurality of first semiconductor structures () of a first type, in particular n+/p−/n−/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (), thereby forming a corresponding plurality of second semiconductor structures () of a second type, in particular n+/n−/p−/n+ structures. The disclosure further relates to a power semiconductor device () comprising a carrier substrate (), at least one dielectric layer (), a plurality of first semiconductor structures () of a first type, and a plurality of second semiconductor structures () of a second type formed within the at least one dielectric layer ().