The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Aug. 21, 2023
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Dong Hun Kwak, Gyeonggi-do, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G06F 3/061 (2013.01); G06F 3/0658 (2013.01); G06F 3/0679 (2013.01); G11C 11/5628 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/40 (2023.02);
Abstract

A memory device may include a memory cell array including memory cells stacked in a direction perpendicular to a substrate, each of the memory cells including a first sub-memory cell and a second sub-memory cell having a size larger than a size of the first sub-memory cell, a sub-memory cell information storage configured to store sub-memory cell size information on the sizes of the first sub-memory cell and the second sub-memory cell, a peripheral circuit configured to perform a program operation on a selected sub-memory cell among the memory cells, and a control logic configured to control the peripheral circuit to store data in each of the first sub-memory cell and the second sub-memory cell based on the sub-memory cell size information.


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