The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Apr. 07, 2022
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Takaaki Iwai, Yokkaichi, JP;

Tomohiro Kubo, Yokkaichi, JP;

Kento Iseri, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/35 (2023.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/27 (2023.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 43/35 (2023.01);
U.S. Cl.
CPC ...
H10B 41/35 (2023.02); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/10 (2023.02); H10B 41/27 (2023.02); H10B 43/10 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02);
Abstract

A three-dimensional memory device includes a source-level structure located over a substrate, an alternating stack of insulating layers and electrically conductive layers located over the source-level structure, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the memory openings. The source-level structure includes a lower source-level semiconductor layer including elongated grooves in an upper portion thereof, doped semiconductor source rails located within the elongated grooves, and an upper source-level semiconductor layer. The doped semiconductor source rails are laterally spaced apart from each other along a first horizontal direction and laterally extend along a second horizontal direction. Each of the memory opening fill structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel that contacts a respective one of the doped semiconductor source rails.


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