The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Dec. 20, 2023
Applicant:

Ipgoal Microelectronics (Sichuan) Co., Ltd., Sichuan, CN;

Inventors:

Yalan Lv, Sichuan, CN;

Xiangyang Guo, Sichuan, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/22 (2006.01); H03K 3/037 (2006.01);
U.S. Cl.
CPC ...
H03K 17/22 (2013.01); H03K 3/037 (2013.01);
Abstract

A power-on reset system includes a reset signal generator, a power-on reset module and a D flip-flop. The reset signal generator generates a reset enable signal when powered on, and the reset enable signal is input to the power-on reset module and the D flip-flop. An output end of the power-on reset module is connected with a clock end of the D flip-flop, an output end of the D flip-flop is connected with a control end of the power-on reset module, and an output signal of the power-on reset module controls the output reset signal of the D flip-flop. When a voltage of the enable end of the power-on reset module is a high level, the power-on reset module is turned off. In such a way, the entire power-on reset system generates no power consumption, thereby improving the working performance of the entire system chip.


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