The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Sep. 27, 2023
Applicant:

Cirrus Logic International Semiconductor Ltd., Edinburgh, GB;

Inventors:

Nishant Jain, Austin, TX (US);

Vamsikrishna Parupalli, Austin, TX (US);

Gaurav Agarwal, Austin, TX (US);

Assignee:

Cirrus Logic Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 3/217 (2006.01); H03F 3/45 (2006.01);
U.S. Cl.
CPC ...
H03F 1/02 (2013.01); H03F 3/217 (2013.01); H03F 3/45071 (2013.01); H03F 2200/129 (2013.01); H03F 2200/414 (2013.01);
Abstract

A system may include a pulse-width modulation mode path configured to drive a load at an output of the system in a first mode of operation, a linear mode path configured to drive the load in a second mode of operation, a common mode control feedback loop configured to set a value of a common mode output signal at the output in the second mode of operation, and an auxiliary circuit coupled to the common mode feedback control loop and configured to maintain a state of the common mode feedback control loop during the first mode of operation as the state was or will be during the second mode of operation.


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