The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jun. 16, 2022
Applicant:

Realtek Semiconductor Corp., Hsinchu, TW;

Inventors:

Chia-Lin Chang, Hsinchu, TW;

Yun-Tse Chen, Hsinchu, TW;

Kai-Yin Liu, Hsinchu, TW;

Cheng-Cheng Yen, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/48 (2013.01); H01L 24/06 (2013.01); H01L 24/49 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/06177 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49112 (2013.01);
Abstract

An electronic package structure and a chip thereof are provided. The electronic package structure includes a supporting element, a chip, an internal bonding wire, and a plurality of external bonding wires. The supporting element has a chip arrangement portion. The chip has a first surface and a second surface opposite to the first surface. The chip is arranged on the chip arrangement portion with the second surface facing toward the supporting element. The chip includes a first common pad and an individual core pad that are disposed on the first surface. The internal bonding wire is connected between the first common pad and the individual core pad. The external bonding wires are connected between the chip and the supporting element, in which a first external bonding wire of the external bonding wires and the internal bonding wire are jointly connected to the first common pad.


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