The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jan. 19, 2023
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Mohd Afiz Hashim, Shah Alam, MY;

Zhi Yuan Goh, Bertam, MY;

Subaramaniym Senivasan, Bemban, MY;

Azmil Abdullah, Merlimau, MY;

Varun Parthasarathy, Johor Bahru, MY;

Kah Wai Lau, Duyung, MY;

Ahmad Zulkarnain Samsudin, Seremban, MY;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01);
U.S. Cl.
CPC ...
H01L 24/40 (2013.01); H01L 23/3107 (2013.01); H01L 23/49517 (2013.01); H01L 24/05 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/05005 (2013.01); H01L 2224/40175 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/73271 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/014 (2013.01);
Abstract

A semiconductor package includes: a substrate having a metallic surface; a semiconductor die metallurgically bonded to the metallic surface of the substrate by a first solder joint; and a solder wetting structure metallurgically welded to the metallic surface of the substrate outside a perimeter of the semiconductor die and adjacent to one or more side faces of the semiconductor die. Excess solder squeezed out from under the semiconductor die is metallurgically bonded to the solder wetting structure. Methods of producing the semiconductor package and solder wetting structure are also described.


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