The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Dec. 29, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Gregory Ostrowicki, Dallas, TX (US);

Amit Nangia, Murphy, TX (US);

Kashyap Mohan, Irving, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 21/565 (2013.01); H01L 23/3121 (2013.01); H01L 23/3135 (2013.01); H01L 24/16 (2013.01); H01L 24/73 (2013.01); H01L 2224/10125 (2013.01); H01L 2224/10155 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17134 (2013.01); H01L 2224/26175 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/351 (2013.01);
Abstract

In examples, a semiconductor package comprises a substrate having multiple conductive layers coupled to bond pads at a surface of the substrate. The package includes a semiconductor die including a device side facing the substrate, the device side having first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region. The package also includes conductive members coupled to the bond pads of the substrate, in direct physical contact with the second circuitry region, and not in direct physical contact with the first circuitry region. The package further comprises a first support member coupled to the device side of the semiconductor die and extending toward the substrate and not touching the substrate or a second support member coupled to the substrate. The package also includes a ring on the substrate and encircling the bond pads and a glob top member covering the semiconductor die and a portion of the substrate circumscribed by the ring. The package also includes a mold compound covering the glob top member and the substrate.


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