The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jun. 15, 2022
Applicant:

Analog Devices, Inc., Wilmington, MA (US);

Inventors:

Ruida Yun, Weston, MA (US);

Dongwan Ha, Arlington, MA (US);

Baoxing Chen, Westford, MA (US);

Assignee:

Analog Devices, Inc., Wilmington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01F 27/29 (2006.01); H01F 27/28 (2006.01); H01F 27/40 (2006.01); H10D 1/20 (2025.01);
U.S. Cl.
CPC ...
H01F 27/2804 (2013.01); H01F 27/2885 (2013.01); H01F 27/29 (2013.01); H01F 27/40 (2013.01); H10D 1/20 (2025.01); H01F 2027/2809 (2013.01);
Abstract

A fully symmetrical and balanced monolithic or multi-die integrated circuit transformer device is described. The device can comprise a first and second transformer. The first and second transformer can each comprise a symmetrical bottom coil including electrically conductive crossovers between individual windings of pairs of adjacent windings. Each of the bottom coils can further comprise a first, a second differential terminal, and a center tap third terminal electrically connected to the inner-most winding of the bottom coil. Each transformer can further comprise a spiral top coil electrically connected to an encompassed inner pad and a laterally offset outer pad, the top coil, inner pad, and outer pad including a shared electrically conductive integrated circuit layer. The respective top coils of each transformer can be overlaid and separated from the respective bottom coils by an electrically insulating dielectric layer.


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