The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Jan. 29, 2024
Applicant:
SK Hynix Inc., Icheon-si, KR;
Inventors:
Chan Keun Kwon, Icheon-si, KR;
Jaehyeong Hong, Icheon-si, KR;
Assignee:
SK hynix Inc., Icheon-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/18 (2006.01); G11C 7/22 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01); G11C 16/32 (2013.01);
Abstract
A memory device may include memory banks comprised of memory blocks; data compressing circuits connected to memory blocks and first merge circuits. A second merge circuit receives output from the first merge circuits. A delay detecting circuit generates delay control signals by comparing the output control signals. A compensating circuit calibrates the output control signals, based on the delay control signal. An output buffer circuit latches the second merged data and outputs the second merged data, based on at least a portion of the output control signals.