The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

Jun. 05, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jin Woo Han, Suwon-si, KR;

Hyun Geun Choi, Suwon-si, KR;

Ki Seok Lee, Suwon-si, KR;

Seok Han Park, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/18 (2006.01); G11C 5/06 (2006.01); G11C 7/12 (2006.01); G11C 11/404 (2006.01); G11C 11/4097 (2006.01); H10B 12/00 (2023.01); G11C 5/02 (2006.01);
U.S. Cl.
CPC ...
G11C 7/18 (2013.01); G11C 5/063 (2013.01); G11C 7/12 (2013.01); G11C 11/404 (2013.01); G11C 11/4097 (2013.01); H10B 12/30 (2023.02); H10B 12/482 (2023.02); H10B 12/50 (2023.02); G11C 5/025 (2013.01);
Abstract

Provided a semiconductor memory device. The semiconductor memory device includes a substrate, a gate electrode on the substrate, a bit line on the substrate, a cell semiconductor pattern on a side of the gate electrode and electrically connected to the bit line, a capacitor structure including a first electrode electrically connected to the cell semiconductor pattern, a second electrode on the first electrode, and a capacitor dielectric film between the first electrode and the second electrode, a bit line strapping line spaced apart from the bit line in the second direction, and electrically connected to the bit line, a bit line selection line between the bit line and the bit line strapping line, and a selection semiconductor pattern between the bit line and the bit line strapping line and electrically connected to all of the bit line, the bit line strapping line, and the bit line selection line.


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