The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Jun. 14, 2022
Xilinx, Inc., San Jose, CA (US);
Ehsan Ghasemi, San Jose, CA (US);
Rajeev Patwari, San Jose, CA (US);
Elliott Delaye, San Jose, CA (US);
Jorn Tuyls, Dublin, IE;
Ephrem C. Wu, San Mateo, CA (US);
Xiao Teng, Cupertino, CA (US);
Sanket Pandit, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Hardware acceleration of machine learning (ML) designs includes translating an ML primitive into an intermediate representation. The intermediate representation is subdivided to specify a functional compute block. The functional compute block is sized according to a compute node primitive adapted for implementing the ML primitive on target hardware. An overlay is generated for the ML primitive, at least in part, by mapping the functional compute block to the compute node primitive. The overlay is synthesizable to implement the ML primitive on the target hardware. The overlay can be scheduled for operation within the target hardware as part of an ML design including the ML primitive.