The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Jul. 01, 2024
SK Hynix Nand Product Solutions Corp., Rancho Cordova, CA (US);
SK Hynix Inc., Icheon-si, KR;
Gulzar Kathawala, Fremont, CA (US);
Ming Zhang, San Jose, CA (US);
Yogesh Wakchaure, Folsom, CA (US);
Jonathan De Vries, Folsom, CA (US);
David Carlton, Pleasanton, CA (US);
Yushin Ahn, Seoul, KR;
Taehun Park, Seoul, KR;
Wanik Cho, Seoul, KR;
SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US);
SK hynix Inc., Icheon-si, KR;
Abstract
In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.