The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Apr. 26, 2024
Dell Products L.p., Round Rock, TX (US);
Brennan Troy Robert Seal, Austin, TX (US);
Chris Everett Peterson, Austin, TX (US);
Nicholas Anthony Esposito, Round Rock, TX (US);
Rachel Gabrielle Mazzini, Dallas, TX (US);
Sandeep Bola Ratnakar, Bangalore, IN;
Siddharth Sreekumar, Bangalore, IN;
Dell Products L.P., Round Rock, TX (US);
Abstract
Method of generating configurations of computing products, including receiving images of a particular layout of the computing product; analyzing the particular layout, including identifying computing components of the computing product and determining a thermal mapping of the computing product; identifying physical constraints associated with the computing components of the computing product; identifying product profile of the computing product that indicates, for each computing component, features of the computing component; iteratively permutating, based on the physical constraints associated with the computing components and the thermal mapping, the particular layout to define permutated layouts; iteratively permutating each of the permutated layouts based on combinations of features of each of the computing components of the particular layout; generating, for the computing component, data table indicating each of the permutated layouts of the computing product and each of the combinations of features of each of the computing components of each of the permutated layouts.