The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2025

Filed:

May. 15, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Martin Langhammer, Alderbury, GB;

Gregg William Baeckler, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 8/41 (2018.01); G06F 9/38 (2018.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 9/30076 (2013.01); G06F 8/44 (2013.01); G06F 9/30058 (2013.01); G06F 9/30098 (2013.01);
Abstract

Integrated circuits that include lightweight processor cores are provided. Each processor core may be configured to execute a series of instructions. At least one of the instructions may include an embedded delay field with a value specifying the amount of time that instruction needs to wait before proceeding to the next instruction to avoid a data hazard. The value of the delay field may be determined by a compiler during software compile time. Such delay field may also be used in conjunction with branch instructions to specify a number of no-operations (NOPs) for one or more associated branch delay slots and may also be used to reduce data forwarding cost.


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