Adaptive tuning of memory device clock rates based on usage workloads

Abstract

Different operations have different clock rate bottleneck points. For example, during a read operation, the processors may be the bottleneck whereas other operations will not be bottlenecks. Those other operations can have their clock rates reduced to save power since there is no benefit to a higher clock rate as the bottleneck is elsewhere. Predicting the bottleneck would be beneficial. Statistics correlating the bottleneck points with the workload and clock rates are tracked. When the workload changes, the statistics can be consulted to determine where the bottleneck is located and then slow down the clock rates for the non-bottleneck operations. A clock rate table is maintained in the device controller. The table holds the clock rate of each component. Predicting the workload and hence, the clock rates, reduces power consumption, improves performance, and better quality of service (QOS) compatibility characteristics.