The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2025
Filed:
Dec. 07, 2022
Hkc Corporation Limited, Shenzhen, CN;
Hongyan Chang, Shenzhen, CN;
Bing Han, Shenzhen, CN;
Shishuai Huang, Shenzhen, CN;
Zhenya Li, Shenzhen, CN;
Guangjia Wang, Shenzhen, CN;
Haoxuan Zheng, Shenzhen, CN;
HKC CORPORATION LIMITED, Shenzhen, CN;
Abstract
The present application relates to an array substrate () and a liquid crystal display panel. The driving array layer of the array substrate () includes a scanning line (G) extending along a first direction (X) and a data line (D) extending along a second direction (Y); the transparent metal layer () includes a first pixel electrode () and a second pixel electrode () which are alternately provided along a first direction (X) and a second direction (Y), and a shielding common electrode () located in an interval region of the first pixel electrode () and the second pixel electrode (); the color-resistance layer () includes color-resistance units () respectively corresponding to the first pixel electrode () and the second pixel electrode (), and in the second direction (Y), a first overlap width (W) between two adjacent color-resistance units () corresponding to the target area is greater than a second overlap width (W) between two adjacent color-resistance units () at the remaining positions in the target area formed by the interval between the first pixel electrode () and the second pixel electrode () intersecting with the scanning line (G). The array substrate can avoid electrical performance problems such as short circuits, crosstalk, etc. due to the remaining underexposed transparent metal layer.