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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12507528 B1

PDFFull Text
Date of Patent:
Dec. 23, 2025

Filed:

May. 25, 2021

Display substrate and manufacturing method thereof, and display device

Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Bo Shi, Beijing, CN;

Chi Yu, Beijing, CN;

Weiyun Huang, Beijing, CN;

Yue Long, Beijing, CN;

Jianchang Cai, Beijing, CN;

Assignees:

CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan, CN;

BEIJING BOE TECHNOLOGY DEVELOPMENT CO., LTD., Beijing, CN;

Attorney:

Scully, Scott, Murphy & Presser, P.C.

Primary Examiner:

Victoria K Hall

Int. Cl.
CPC ...
H10K 59/131 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/124 (2023.01); H10K 59/126 (2023.01); H10K 59/50 (2023.01); H10K 59/65 (2023.01); H10K 59/80 (2023.01); H10K 71/60 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); H10K 59/1201 (2023.02); H10K 59/124 (2023.02); H10K 59/126 (2023.02); H10K 59/131 (2023.02); H10K 59/50 (2023.02); H10K 59/65 (2023.02); H10K 59/8792 (2023.02); H10K 71/60 (2023.02); H10K 59/805 (2023.02);
Abstract

A display substrate, a manufacturing method thereof and a display device are provided. The display substrate includes: a base substrate; a first conductive element located on the base substrate; a first planarization layer located on the first conductive element; a second conductive element located on the first planarization layer and connected to the first conductive element through a first via hole penetrating through the first planarization layer; a second planarization layer located on the second conductive element; and a conductive line located on the second planarization layer; the second conductive element is recessed at the first via hole, the second planarization layer has a light-shielding portion, and an orthographic projection of the first via hole on the base substrate falls within an orthographic projection of the light-shielding portion on the base substrate.

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