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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12507525 B1

PDFFull Text
Date of Patent:
Dec. 23, 2025

Filed:

Dec. 14, 2021

Display apparatus, electronic device, and method for manufacturing display apparatus

Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Inventors:

Daiki Nakamura, Kanagawa, JP;

Rai Sato, Tochigi, JP;

Ryu Kokubo, Tochigi, JP;

Hiroki Adachi, Tochigi, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi, JP;

Attorney:

Fish & Richardson P.C.

Primary Examiner:

Donald L Raleigh

Int. Cl.
CPC ...
H10K 59/12 (2023.01); H10K 50/15 (2023.01); H10K 50/16 (2023.01); H10K 59/38 (2023.01); H10K 59/80 (2023.01); H10K 71/60 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1201 (2023.02); H10K 50/15 (2023.02); H10K 50/16 (2023.02); H10K 59/38 (2023.02); H10K 59/8051 (2023.02); H10K 59/8052 (2023.02); H10K 71/60 (2023.02);
Abstract

A method for manufacturing a display apparatus having high display quality is provided. A method for manufacturing a display apparatus including first to third insulators, first and second conductors, and first and second EL layers is provided. The first conductor is formed over the first insulator, and the second insulator is formed over the first insulator and over the first conductor. A first opening portion reaching the first conductor is formed in the second insulator. A sacrificial layer is formed over the second insulator and over a bottom surface of the first opening portion, and a resist is applied over the sacrificial layer. Light exposure and development are performed on the resist, so that a second opening portion reaching the sacrificial layer is formed in a region overlapping with the first conductor. A third opening portion is formed in a region of a bottom surface of the second opening portion, and the first EL layer is formed over the resist, over the sacrificial layer, and over the first conductor. Then, the resist and the sacrificial layer are removed, whereby the first EL layer over the resist and over the sacrificial layer is removed. The second EL layer is formed over the first EL layer and over the second insulator, and the second conductor and the third insulator are formed in order over the second EL layer.

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