The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Feb. 23, 2022
Applicant:

Fuji Electric Co., Ltd., Kanagawa, JP;

Inventor:

Motoyoshi Kubouchi, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 12/00 (2025.01); H10D 8/00 (2025.01); H10D 8/01 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01);
U.S. Cl.
CPC ...
H10D 12/481 (2025.01); H10D 8/01 (2025.01); H10D 8/422 (2025.01); H10D 62/127 (2025.01); H10D 62/393 (2025.01);
Abstract

Provided is a semiconductor device in which a lifetime control region including a lifetime killer is provided, below a base region, from at least a part of a transistor portion to a diode portion, the transistor portion includes: a main region spaced apart from the diode portion in a top view; a boundary region located between the main region and the diode portion and overlapping the lifetime control region in a top view; and a plurality of gate trench portions provided from an upper surface of the semiconductor substrate to a drift region through the base region, the plurality of gate trench portions include: a first gate trench portion provided in the main region; and a second gate trench portion provided in the boundary region, and a signal transmission timing of the first gate trench portion is different from a signal transmission timing of the second gate trench portion.


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