The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jun. 17, 2021
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Hyukje Kwon, Seoul, KR;

Byungyong Choi, Seongnam-si, KR;

Jisang Lee, Iksan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 43/40 (2023.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); H10B 41/27 (2023.01); H10B 41/41 (2023.01); H10B 43/27 (2023.01);
U.S. Cl.
CPC ...
H10B 43/40 (2023.02); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); H10B 41/27 (2023.02); H10B 41/41 (2023.02); H10B 43/27 (2023.02);
Abstract

A memory device includes a cell region in which memory blocks, respectively including gate electrodes and insulating layers, alternately stacked on a substrate, and channel structures, extending in a first direction, perpendicular to an upper surface of the substrate, passing through the gate electrodes and the insulating layers, and connected to the substrate, are arranged. A peripheral circuit region includes a row decoder connected to the gate electrodes and a page buffer connected to the channel structures. The memory blocks include main blocks and at least one spare block, wherein a length of the spare block is shorter than a length of each of the main blocks, in a second direction, parallel to the upper surface of the substrate.


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