The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Sep. 05, 2024
Applicant:

Nxp B.v., Eindhoven, NL;

Inventors:

Philippe Christian Belin, Mezidon Vallée d'Auge, FR;

Laurent Gambus, Cuverville, FR;

Mathieu Périn, Cairon, FR;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01); H03L 7/093 (2006.01); H03L 7/107 (2006.01);
U.S. Cl.
CPC ...
H03L 7/099 (2013.01); H03L 7/093 (2013.01); H03L 7/1075 (2013.01);
Abstract

A method of operation for a dual mode Phase-Locked Loop (PLL) for phase coherent application includes selecting one of a non-coherent mode and a coherent mode. The non-coherent mode includes controlling a Voltage Controlled Oscillator (VCO) with a first error voltage determined by a first Low Pass Filter (LPF), the first LPF configured to filter a first output of a phase detector, the phase detector configured to determine a phase difference between a reference frequency and a feedback signal derived from a VCO frequency generated by the VCO. The coherent mode includes controlling the VCO with the first error voltage and a second error voltage determined by a second LPF of a Proportional and Integral Controller (PIC) configured to filter the first output of the phase detector and by a time variant proportional gain configured to modify a second output of the second LPF.


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