The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jul. 03, 2023
Applicant:

Sandisk Technologies, Inc., Milpitas, CA (US);

Inventors:

Alvin Joshua, Fujisawa, JP;

Hardwell Chibvongodze, Hiratsuka, JP;

Yuki Kuniyoshi, Fujisawa, JP;

Akitomo Nakayama, Yokohama, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0185 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 3/356113 (2013.01);
Abstract

On memory die and other circuits, some parts may operate at a VDD logic level while other elements operate at a higher logic level, such as at or near the die's supply level VSUP. To reduce power consumption and increase operating speeds, VDD levels are moving to increasingly lower voltages. To raise the logic signal from the lower level to the higher, level shifters can be used. However, as the gap between the supply level VSUP and VDD widens, it can become difficult for a level shifter to reliably raise a logic signal operating at the VDD level to the VSUP level. The address this problem, the following introduces a small charge pump to boost the input logic signals for level shifter circuits to allow them to reliably generate an output logic signal at the VSUP level from an input logic signal at low VDD levels.


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