The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jan. 25, 2024
Applicant:

Infineon Technologies Canada Inc., Ottawa, CA;

Inventors:

Lucas Andrew Milner, Sunnyvale, CA (US);

Ramesh G. Karpur, Bangalore, IN;

Abhishek Jain, Delhi, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/06 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H03K 17/063 (2013.01); H03K 17/6871 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

A circuit for providing an alternating signal to a switching node. The circuit includes three power transistors, two capacitors, and two gate drivers. The first and second transistors are connected in series, with the switching node connected therebetween. When the first transistor is on and the second transistor is off, a high voltage is provided to the switching node via the first transistor. When the first transistor is off and the second transistor is on, a low voltage is provided to the switching node via the second transistor. The transistors are controlled via the gate drivers. Charge is provided to the gate drivers via the capacitors. The capacitors are charged via an intermediate power source, with the third power transistor connected in diode configuration between the two capacitors. The circuit is capable of withstanding high voltage differences across the transistors, and may be implemented monolithically on a same epitaxial stack.


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