The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Oct. 31, 2023
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Partha Mondal, Paschim Medinipur, IN;

Arun Khamesra, Bangalore, IN;

Santosh Kulkarni, Dharwad, IN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/335 (2006.01);
U.S. Cl.
CPC ...
H02M 3/33592 (2013.01);
Abstract

A flyback-converter with synchronous-rectifier (SR) sense architecture is provided. A secondary side controller includes a SR-sense pin coupled through an external resistor to a drain of an SR on the secondary-side, a negative-sensing-detector, a peak-detector, a zero-crossing-detector, all coupled to the pin, and a resistor network (Rn) coupled between the pin and ground. The Rn includes a first resistor (R) to couple the pin and to ground through a first switch (S) during negative-sensing to divide a voltage (V) coupled to the pin, and a second, higher resistance resistor (R) to couple the pin to ground through a second switch (S) during peak-detection to divide Vcoupled to the pin. Sand Sare controlled by register-transfer-level circuit in the SSC. A line-feed-forward (LFF) circuit is coupled to the pin through an active diode to receive an undivided Vand mirrors diode current to control the converter in LFF mode.


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