The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Dec. 19, 2023
Applicant:

Len Tech Inc., Plano, TX (US);

Inventor:

Chuan Ni, Plano, TX (US);

Assignee:

LEN TECH Inc., Plano, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 1/00 (2006.01); H02M 1/088 (2006.01); H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
H02M 1/088 (2013.01); H02M 1/0058 (2021.05); H02M 3/158 (2013.01); H03K 17/163 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

A hybrid power transistor apparatus includes a first switching element comprising a first number of transistor cells connected in parallel between a first terminal and a second terminal of the apparatus, wherein gates of the first number of transistor cells are connected together, and the gates of the first number of transistor cells are connected to an output of a first gate drive circuit, and a second switching element comprising a second number of transistor cells connected in parallel between the first terminal and the second terminal of the apparatus, wherein gates of the second number of transistor cells are connected together, and the gates of the second number of transistor cells are connected to an output of a second gate drive circuit, and wherein a delay is placed between the output of the first gate drive circuit and the output of the second gate drive circuit.


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