The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jan. 02, 2024
Applicant:

Etel S.a., Motiers, CH;

Inventor:

Piotr Zimoch, Scherz, CH;

Assignee:

ETEL S.A., Motiers, CH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 1/00 (2006.01); H02M 3/00 (2006.01); H03K 17/06 (2006.01);
U.S. Cl.
CPC ...
H02M 1/0006 (2021.05); H02M 3/005 (2013.01); H02M 3/158 (2013.01); H03K 17/063 (2013.01); H03K 2217/0063 (2013.01); H03K 2217/0072 (2013.01);
Abstract

A half-bridge converter includes a high-side transistor connected to a positive electrode of a direct current (DC) voltage source and a low-side transistor connected to a reference ground. A gate driver is configured to control the high-side and low-side transistors at a duty cycle of a gate driver control signal. A bootstrap circuit is configured to provide a positive voltage and a negative voltage to the gate driver for the high-side transistor. The bootstrap circuit comprises a first diode, a first capacitor and a Cuk converter. The Cuk converter comprises a first and a second inductor, a switch, a first and a second capacitor and a second diode to output the negative voltage to the high-side transistor gate driver. The Cuk converter is configured to output the negative voltage when operating in a Discontinuous Voltage Mode (DVM).


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