The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Sep. 29, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kihun Oh, Suwon-si, KR;

Gwanghyun Jung, Suwon-si, KR;

Yonghee Cho, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2023.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01); H10H 20/857 (2025.01);
U.S. Cl.
CPC ...
H01L 25/167 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H10H 20/857 (2025.01); H01L 23/5384 (2013.01); H01L 24/17 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/29147 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/73204 (2013.01);
Abstract

A display is provided. The display includes a first substrate comprising a plurality of electrode pads disposed on a front surface, a plurality of solder members disposed on a rear surface, and a plurality of wiring members electrically connecting the plurality of electrode pads and the plurality of solder members, respectively, a plurality of light-emitting elements electrically connected to each of the plurality of electrode pads, and constituting pixels of two columns, and a second substrate comprising a thin film transistor (TFT) layer disposed on a rear side of the first substrate and electrically connected to the plurality of solder members to control driving of the plurality of light-emitting elements, and the first substrate may include a first region in which pixels of a first column are disposed, a second region in which pixels of a second column are disposed, and a third region disposed between the first region and the second region, the plurality of wiring members may be disposed on the first region and the second region among the front surface of the first substrate.


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