The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Aug. 01, 2023
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Yeong Jo Mun, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3427 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); G11C 16/3459 (2013.01);
Abstract

A semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers each performing an auxiliary verify operation and a main verify operation, which are used to program selected memory cells among the plurality of memory cells; and control logic for controlling the auxiliary verify operation and the main verify operation of the peripheral circuit. During the main verify operation, the control logic controls the peripheral circuit to selectively precharge sensing nodes of the plurality page buffers respectively corresponding to the selected memory cells, based on a result of the auxiliary verify operation.


Find Patent Forward Citations

Loading…