The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 2025
Filed:
Mar. 29, 2023
Beijing Boe Display Technology Co., Ltd., Beijing, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Yang Wang, Beijing, CN;
Yi Liu, Beijing, CN;
Gongda Chen, Beijing, CN;
Jiantao Liu, Beijing, CN;
Haiyao Liang, Beijing, CN;
Shijun Wang, Beijing, CN;
Zhan Wei, Beijing, CN;
Tengfei Ding, Beijing, CN;
Shengfeng Zhang, Beijing, CN;
Xinlan Yang, Beijing, CN;
Shengmei Qi, Beijing, CN;
Yuke Tai, Beijing, CN;
Jiguo Wang, Beijing, CN;
Zhou Peng, Beijing, CN;
Zhangjie Qiu, Beijing, CN;
Beijing BOE Display Technology Co., Ltd., Beijing, CN;
Beijing BOE Technology Development Co., Ltd., Beijing, CN;
Abstract
An array substrate, a shift register unit and a display apparatus are provided. The array substrate includes data lines, gate lines, first control signal lines and sub-pixels. The sub-pixel includes a first sub-pixel portion including a first pixel electrode and a first transistor, and a second sub-pixel portion including a second pixel electrode, a second transistor and a third transistor; the first transistor is connected with the first pixel electrode the second transistor and the third transistor are connected with the second pixel electrode, the first transistor and the second transistor are connected with a same gate line and a same data line, and the third transistor is connected with the first control signal line. The second sub-pixel portion includes an adjustable capacitor connecting with the third transistor, and the array substrate further includes a second control signal line connected with the adjustable capacitor.