The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jun. 05, 2020
Applicant:

Nec Corporation, Tokyo, JP;

Inventors:

Akira Miyata, Tokyo, JP;

Katsumi Kikuchi, Tokyo, JP;

Suguru Watanabe, Tokyo, JP;

Takanori Nishi, Tokyo, JP;

Hideyuki Satou, Tokyo, JP;

Tomohiro Yamaji, Tokyo, JP;

Tsuyoshi Yamamoto, Tokyo, JP;

Yoshihito Hashimoto, Tokyo, JP;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 10/40 (2022.01); G01R 33/035 (2006.01);
U.S. Cl.
CPC ...
G06N 10/40 (2022.01); G01R 33/0354 (2013.01);
Abstract

Provided is a quantum device capable of suppressing reduction in performance of quantum bit even when a quantum chip is flip-chip mounted on an interposer. A quantum chip () is flip-chip mounted on an interposer () by a bump (). A coplanar line () coupling adjacent quantum bits is formed on the quantum chip (). A gap () is provided, in the interposer (), at a location facing a center conductor () of the coplanar line (). A second ground electrode () is formed around gap (). The interposer () has a connection electrode () connecting the second ground electrode () around the gap (). A bump (A) formed in the vicinity of the connection electrode () is connected to the first ground electrode () and the second ground electrode ().


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