The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 23, 2025

Filed:

Jul. 27, 2020
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Bharadwaj Pudipeddi, San Jose, CA (US);

Juliana Patrícia Vicente Franco, Cambridge, GB;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2023.01); G06F 12/06 (2006.01); G06N 3/04 (2023.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 12/0646 (2013.01); G06N 3/04 (2013.01); G06F 2212/251 (2013.01);
Abstract

Embodiments of the present disclosure include systems and methods for training neural networks. In one embodiment, data for an artificial intelligence model is processed in a first plurality of stages and in a second plurality of stages. The first and second pluralities of stages form a pipeline. One or more of the first plurality of stages uses at least one memory associated with a corresponding one or more of the second plurality of stages to balance memory across the pipeline.


Find Patent Forward Citations

Pudipeddi, Bharadwaj. (2025). Stash balancing in model parallelism (U.S. Patent No. 12505340). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12505340

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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