Semiconductor device and method of scan test for thereof

Abstract

In scan testing of semiconductor devices, instantaneous power consumption in both shift and capture modes is efficiently reduced. The scan chain is provided with circuit blocksto. Each of the temporary storage flip-flops Fto Fis connected between one of the two circuit blocks. Clock generating circuitoutputs a clock signal CLK used for the scan test. The clock gating cells GCto GCtakes the clock signal CLK and provides the clock signals CLKto CLKto circuit blockstoand the clock signals CLKto CLKto the temporary storage flip-flops Fto F. The control circuitcontrols the clock gating cells GCto GCso as to operate the circuit blockstoat differing timings from the input-side one by one and simultaneously operate each circuit block and a temporary storage flip-flop connected to the output of each circuit block.