logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12501786 B1

PDFFull Text
Date of Patent:
Dec. 16, 2025

Filed:

Nov. 04, 2021

Display substrate and preparation method thereof, and display apparatus

Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Jiayu He, Beijing, CN;

Ce Ning, Beijing, CN;

Zhengliang Li, Beijing, CN;

Hehe Hu, Beijing, CN;

Fengjuan Liu, Beijing, CN;

Wei Liu, Beijing, CN;

Tianmin Zhou, Beijing, CN;

Kun Zhao, Beijing, CN;

Assignee:

Beijing BOE Technology Development Co., Ltd., Beijing, CN;

Attorneys:

Ling Wu

Stephen Yang

Ling and Yang Intellectual Property

Primary Examiner:

Victoria K Hall

Int. Cl.
CPC ...
H10K 59/124 (2023.01); H10D 30/67 (2025.01); H10K 39/34 (2023.01); H10K 59/12 (2023.01); H10K 59/121 (2023.01); H10K 59/13 (2023.01); H10K 59/60 (2023.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01);
U.S. Cl.
CPC ...
H10K 59/124 (2023.02); H10D 30/6704 (2025.01); H10D 30/6734 (2025.01); H10K 39/34 (2023.02); H10K 59/1201 (2023.02); H10K 59/1213 (2023.02); H10K 59/13 (2023.02); H10K 59/60 (2023.02); H10D 30/6755 (2025.01); H10D 86/423 (2025.01); H10D 86/60 (2025.01);
Abstract

The present disclosure provides a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a circuit layer disposed on a base substrate, an emitting structure layer and a photoelectric structure layer disposed on a side of the circuit layer away from the base substrate, the circuit layer includes at least one impurity absorption layer and at least one transistor, the transistor includes an active layer, and at least one insulation layer is provided between the impurity absorption layer and the active layer; an atomic ratio of a silicon element to a nitrogen element in the impurity absorption layer is 1:5 to 1:35.

Find Patent Forward Citations

Loading…