The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Feb. 12, 2020
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Yunsheng Xiao, Beijing, CN;

Xiangdan Dong, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/32 (2006.01); H10K 59/122 (2023.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01);
U.S. Cl.
CPC ...
H10K 59/122 (2023.02); H10K 59/131 (2023.02); H10K 71/00 (2023.02); H10K 59/1201 (2023.02);
Abstract

The present disclosure provides a display panel and a manufacturing method thereof, and a display device. The display panel includes a display area and a non-display area surrounding the display area; the display panel structurally includes a substrate, and a buffer layer, a semiconductor layer, a first inorganic insulating layer, a first metal layer, a second inorganic insulating layer, a second metal layer, a third inorganic insulating layer, a third metal layer, a first organic layer, an anode layer, a pixel defining layer, an organic functional layer and a cathode layer which are located on one side of the substrate and arranged in sequence in a direction away from the substrate; wherein: the non-display area includes a circuit-board bonding area, in which there is a gap between both a boundary of the first organic layer and a boundary of the pixel defining layer and the boundary of the substrate.


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