The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Feb. 06, 2024
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Ying Han, Beijing, CN;

Pan Xu, Beijing, CN;

Xing Zhang, Beijing, CN;

Donghui Zhao, Beijing, CN;

Guangshuang Lv, Beijing, CN;

Chengyuan Luo, Beijing, CN;

Cheng Xu, Beijing, CN;

Hongli Wang, Beijing, CN;

Tong Wu, Beijing, CN;

Dandan Zhou, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); H10K 59/121 (2023.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1213 (2023.02); G09G 3/3233 (2013.01); H10K 59/131 (2023.02); G09G 2300/0426 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0233 (2013.01);
Abstract

The present application provides a display panel and a semiconductor device. The display panel is provided with a plurality of pixel light-emitting units and a plurality of driving circuits. An active layer is located on one side of a substrate and comprises a plurality of active regions. A first gate layer comprises a plurality of gates, and there is an overlapping area between the orthographic projections of the gates on the substrate and the orthographic projections of the corresponding active regions on the substrate. A second gate layer is located on the side of the first gate layer distant from the active layer and comprises a shielding layer. A first source-drain electrode layer is located on the side of the second gate layer distant from the first gate layer, and comprises a plurality of power lines arranged side by side.


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