The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Mar. 02, 2023
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Teruyuki Ohashi, Kawasaki Kanagawa, JP;

Tatsuo Shimizu, Tokyo, JP;

Hiroshi Kono, Himeji Hyogo, JP;

Shunsuke Asaba, Himeji Hyogo, JP;

Takahiro Ogata, Kawasaki Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/83 (2025.01); H10D 8/60 (2025.01); H10D 62/832 (2025.01); H10D 84/00 (2025.01);
U.S. Cl.
CPC ...
H10D 62/8325 (2025.01); H10D 8/60 (2025.01); H10D 84/146 (2025.01);
Abstract

A semiconductor device according to an embodiment includes a transistor region and a diode region. The transistor region includes n-type first SiC region having a first portion contacting a first plane, p-type second SiC region, n-type third SiC region, and a gate electrode. The diode region includes the first SiC region having a second portion contacting the first plane and p-type fourth SiC region. The semiconductor device includes a first electrode contacting the first portion and the second portion and a second electrode contacting a second plane. An occupied area per unit area of the fourth SiC region is larger than an occupied area per unit area of the second SiC region. In addition, a first diode region is provided between a first transistor region and a second transistor region. An inorganic insulating layer is provided between the first electrode and a gate wiring adjacent to the first electrode.


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