The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jun. 14, 2022
Applicant:

Suzhou Oriental Semiconductor Co., Ltd., Jiangsu, CN;

Inventors:

Wei Liu, Jiangsu, CN;

Lei Liu, Jiangsu, CN;

Yuanlin Yuan, Jiangsu, CN;

Rui Wang, Jiangsu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/66 (2025.01);
U.S. Cl.
CPC ...
H10D 62/111 (2025.01); H10D 30/66 (2025.01);
Abstract

A super junction semiconductor power device includes an n-type drain region, an n-type drift region, multiple p-type columns, a gate structure, and multiple JFET regions. The width of each of the multiple p-type columns is equal. The spacing between two adjacent p-type columns is equal. The tops of the multiple p-type columns are provided with multiple p-type body regions respectively, and the p-type body regions are in one-to-one correspondence with the p-type columns. The widths of the multiple p-type body regions are equal. An n-type source region is provided in each p-type body region. The gate structure is configured to control a current channel between the n-type source region and the n-type drift region to turn on and turn off. The multiple JFET regions are located on the n-type drift region and between adjacent p-type body regions. The multiple JFET regions are provided with at least two different widths.


Find Patent Forward Citations

Loading…