The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Dec. 07, 2022
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventor:

Masatsugu Yutani, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01);
U.S. Cl.
CPC ...
H10D 30/668 (2025.01); H10D 62/102 (2025.01); H10D 62/393 (2025.01);
Abstract

A semiconductor device includes: a semiconductor layer; a gate trench formed in the semiconductor layer; an insulating layer formed on the semiconductor layer; a gate electrode buried in the gate trench via the insulating layer; a gate wiring formed on the insulating layer and electrically connected to the gate electrode; and a protection trench formed in the semiconductor layer, wherein the semiconductor layer includes an outer peripheral region including outer edges of the semiconductor layer in a plan view and an inner region surrounded by the outer peripheral region, wherein the gate trench includes an outer peripheral gate trench portion arranged in the outer peripheral region and surrounded by the protection trench in a plan view, and wherein the outer peripheral gate trench portion and the protection trench are formed in a closed annular shape along the outer edges of the semiconductor layer in the outer peripheral region.


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