The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Jul. 05, 2022
Applicant:

Institute of Microelectronics, Chinese Academy of Sciences, Beijing, CN;

Inventor:

Huilong Zhu, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 51/20 (2023.01); G11C 16/04 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 43/10 (2023.01); H10B 43/27 (2023.01); H10B 51/10 (2023.01);
U.S. Cl.
CPC ...
H10B 43/27 (2023.02); G11C 16/0483 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 43/10 (2023.02); H10B 51/10 (2023.02); H10B 51/20 (2023.02);
Abstract

Disclosed are a NOR-type memory device, a method of manufacturing the NOR-type memory device, and an electronic apparatus. The NOR-type memory device includes: a memory device layer, including a first source/drain region, a second source/drain region and a first channel region; a first gate stack extending vertically to pass through the memory device layer and including a first gate conductor layer and a memory functional layer, and a memory cell is defined at an intersection of the first gate stack and the memory device layer; a selection device layer on the memory device layer, including a third source/drain region, a fourth source/drain region and a second channel region; a second gate stack above the first gate stack and extending vertically to pass through the selection device layer; and a connecting portion electrically connecting the third source/drain region to the first gate conductor layer.


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