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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12500167 B1

PDFFull Text
Date of Patent:
Dec. 16, 2025

Filed:

May. 03, 2023

Semiconductor device and data storage system including the same

Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Minkyu Chung, Suwon-si, KR;

Sangjae Lee, Suwon-si, KR;

Seungyoon Kim, Suwon-si, KR;

Jaehwang Sim, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, KR;

Attorney:

Muir Patent Law, PLLC

Primary Examiner:

Herve-Louis Y Assouman

Int. Cl.
CPC ...
H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 25/065 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 41/40 (2023.01); H10B 41/50 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 43/50 (2023.01); H10B 51/20 (2023.01); H10B 51/30 (2023.01); H10B 51/40 (2023.01); H10B 63/00 (2023.01); H10B 63/10 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/5283 (2013.01); H01L 23/5226 (2013.01); H01L 25/0652 (2013.01); H10B 41/27 (2023.02); H10B 41/35 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/35 (2023.02); H10B 43/40 (2023.02); H10B 80/00 (2023.02);
Abstract

A semiconductor device may include a first structure, a second structure on the first structure, and gate contact plugs penetrating through the first and second structures. The first structure may include a first stack structure including first gate layers and first insulating layers alternately stacked, a first pad capping pattern penetrating through at least a first portion of the first stack structure, and a first buffer capping pattern penetrating through at least a second portion of the first stack structure and spaced apart from the first pad capping pattern. The second structure may include a second stack structure including second gate layers and second insulating layers alternately stacked, and a second pad capping pattern penetrating through at least a portion of the second stack structure. The first gate layers may include first gate pads covered by the first pad capping pattern.

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