Sense amplifier, operating method thereof, and volatile memory device including the same

Abstract

Disclosed is a sense amplifier which includes a sense amplification circuit and a sensitivity control circuit. The sense amplification circuit includes first and second MOS transistors. The first MOS transistor is connected with a first bit line and a target memory cell. The second MOS transistor is connected with a second bit line and a non-target memory cell. The sense amplification circuit pre-charges the first and second bit lines with a first driving voltage, compensates for an offset, and senses the target data based on a change in a voltage level of the first bit line, after charge sharing between the target memory cell and the first bit line. The sensitivity control circuit adjusts the sensing sensitivity for the target data indicating a first logical value by increasing a magnitude of a current flowing through the first MOS transistor while the sense amplification circuit senses the target data.